TSMC Skips Hybrid Bonding For Now, Betting on Conventional Microbumps to Lead The Way
Supply-chain sources claim TSMC is skipping hybrid bonding for now and will instead push 5µm microbumps for chip packaging. Mass production is expected by second half of 2028, and TSMC is collaborating with South Korean and Japanese suppliers.
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AI CuratedThe current state of Hybrid Bonding in 2026 — TSMC sits at 6 microns and the HBM delay that nobody expected
Tom's Hardware examines the state of hybrid bonding in 2026: TSMC's SoIC pitch roadmap from 9 to 6 microns with 4.5-micron by 2029, Intel's Foveros Direct in volume on Clearwater Forest, and AMD's use in 3D V-Cache and MI300. A JEDEC decision raising HBM stack height lets HBM4 stay on microbumps, deferring hybrid bonding in memory to HBM4E and HBM5, while memory makers build advanced packaging capacity ahead of deployment.
Intel’s David Zinsner Says 14A Improving Fastest Since 2012 Node, Betting Foundry’s Future On TSMC Fight
Intel's CFO at Deutsche Bank conference discusses 14A defect density and its importance to Intel's foundry ambitions against TSMC.
SK hynix Eyes Intel Foundry for HBM4E Base Die Manufacturing
The South Korean Herald reports that SK hynix is considering Intel Foundry as a second supplier for HBM4E base dies, alongside TSMC. This would allow custom logic on the base die. The article is based on a rumor but has a credible source.