Nvidia Confirmed to be intentionally artificially locking DLSS 5 to Blackwell GPUs to boost sales.
A Reddit post in r/hardware summarizes a TechPowerUp article confirming that Nvidia intentionally locks DLSS 5 to RTX 50-series Blackwell GPUs. The article quotes Nvidia stating DLSS 5 is for RTX 50 only, while modders have already run it on RTX 40 series and older architectures with similar performance. The post highlights the artificial limitation and Nvidia's refusal to provide a legacy fallback path, citing direct confirmation from the company.
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AI CuratedHardware Unboxed Falls Victim to Melted RTX 5090 Power Connector as Cable Reaches 175°C
TechPowerUp reports that Hardware Unboxed experienced a melted 12V-2×6 power connector on an ASUS ROG Astral RTX 5090 paired with a be quiet! Dark Power 13 PSU. The cable reached 175°C under load, and a Thermal Grizzly WireView Pro revealed a severe current imbalance where one wire carried ~22A while others carried almost nothing. Damage was worse on the PSU side, with the cable fused inside the connector. The incident is not isolated, as multiple RTX 5090 connector melting cases have been reported even with undervolts and power limits.
TSMC Delays Hybrid Bonding Investment for HBM, Opts for Microbumps
ETNews sources say TSMC will keep HBM attached via microbumps rather than move to hybrid bonding, shrinking bumps to 5 micrometers with mass production targeted for H2 2028. The report frames this as a packaging technology decision affecting future GPU/HBM integration.
ASUS and Galax Raise GeForce RTX 50-Series Prices by Up to $74
Citing a Channel Gate report, ASUS is increasing RTX 5070 prices by $22-$44 and Galax is raising RTX 5070, 5070 Ti, and 5080 prices by about $30-$74. The hikes follow earlier 2026 GDDR7-driven increases, and other board partners may follow.
The current state of Hybrid Bonding in 2026 — TSMC sits at 6 microns and the HBM delay that nobody expected
Tom's Hardware examines the state of hybrid bonding in 2026: TSMC's SoIC pitch roadmap from 9 to 6 microns with 4.5-micron by 2029, Intel's Foveros Direct in volume on Clearwater Forest, and AMD's use in 3D V-Cache and MI300. A JEDEC decision raising HBM stack height lets HBM4 stay on microbumps, deferring hybrid bonding in memory to HBM4E and HBM5, while memory makers build advanced packaging capacity ahead of deployment.